Related Content: CS604 - VU Lectures, Handouts, PPT Slides, Assignments, Quizzes, Papers & Books of Operating Systems
In paged segmentation, we divide every segment in a process into fixed size pages.
We need to maintain a page table per segment CPU’s memory management unit must
support both segmentation and paging. The following snapshots illustrate these points.
The logical address is still <s,d>, with s used to index the segment table. Each segment table entry consist of the tuple
<segment-length, page-table-base>
The logical address is legal if d < segment-length. The segment offset, d, is partitioned into two parts: p and d’, where p is used to index the page table associated with the segment s and d’ is used as offset within the page p. p indexes the page table to retrieve frame, f, and physical address (f,d’) is formed. The following diagrams show the format of logical address and its division, and the hardware support needed for logical to physical address translation.
We now take the example of one of the finest operating systems of late 1960s and early 1970s, known as the MULTICS operating system. Here are the specifications of the CPU supported by MULTICS and calculation of its various parameters such as the largest segment size supported by MULTICS.
Logical address and its partition for GE645 on which MULTICS ran
Consider a process with its segment 15 having 5096 bytes. The process generates a
logical address (15,3921). Is it a legal address? How many pages does the segment have?
What page does the logical address refer to? Is it a legal address? Yes
Logical/virtual address and its division for Intel 80386 and higher
20-bit physical address is obtained by shifting left the Selector value by four bits and adding to it the 16-bit effective address.