# CS604 - Operating Systems - Lecture Handout 36

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## Summary

• Paged segmentation
• Examples of paged segmentation: MULTICS under GE 345 and OS/2, Windows, and Linux under Intel CPUs

## Paged Segmentation

In paged segmentation, we divide every segment in a process into fixed size pages.
We need to maintain a page table per segment CPU’s memory management unit must support both segmentation and paging. The following snapshots illustrate these points.

The logical address is still <s,d>, with s used to index the segment table. Each segment table entry consist of the tuple

<segment-length, page-table-base>

The logical address is legal if d < segment-length. The segment offset, d, is partitioned into two parts: p and d’, where p is used to index the page table associated with the segment s and d’ is used as offset within the page p. p indexes the page table to retrieve frame, f, and physical address (f,d’) is formed. The following diagrams show the format of logical address and its division, and the hardware support needed for logical to physical address translation.

## MULTICS Example

We now take the example of one of the finest operating systems of late 1960s and early 1970s, known as the MULTICS operating system. Here are the specifications of the CPU supported by MULTICS and calculation of its various parameters such as the largest segment size supported by MULTICS.

• GE 345 processor
• Logical address = 34 bits
• Page size = 1 KB
• s is 18 bits and d is 16 bits
• Size of p and d’, largest segment size, and max. number of segments per process?
• Largest segment =
• Maximum number of pages per segment =
• |p| = log2 64 bits = 6 bits
• |d’| = log2 1 K = 10 bits
• Maximum number of segments per process =

Logical address and its partition for GE645 on which MULTICS ran

Consider a process with its segment 15 having 5096 bytes. The process generates a logical address (15,3921). Is it a legal address? How many pages does the segment have?
What page does the logical address refer to? Is it a legal address? Yes

• How many pages does the segment have?
ceiling[5096/1024]= 5
• What page does the logical address refers to?
ceiling[3921/1024]= 4 (i.e., page number 3)
• What are the value of d’ and the physical address if page number 3 (i.e., the fourth page) is in frame 12? Here is how we compute these parameters, along with the graphical representation of the various parameters. Logical to physical address translation is shown in the figure on the next page.

• IBM OS/2, Microsoft Windows, and Linux run on it
• Paged segmentation with two-level paging
• Logical address = 48 bits
• 16-bit selector and 32-bit offset
• Page size = 4 KB
• 4-byte page table entry
• 32-entry TLB, covering 32*4K (128 KB) memory … TLB Reach

Logical/virtual address and its division for Intel 80386 and higher

## Real Mode

20-bit physical address is obtained by shifting left the Selector value by four bits and adding to it the 16-bit effective address.